Gate-level simulation on a GPU

Gate-level simulation for billion-gate designs, on one GPU or several.

Xerolane simulates synthesized gate-level netlists on one GPU, running many vectors at the same time. 640,000 vectors through a 16.2-million-gate design take 16.6 seconds on a laptop. Test generation runs on the same engine: a 206-million-gate design reaches 99.5% test coverage on the same laptop.

Run your netlist See the numbers

one netlist · many vectors at once4-state · 0 1 X Z

Each row is an independent vector on the same netlist, all simulated at the same time. Hatched cycles are X, before reset resolves the state.

Simulation

16.6s

640,000 vectors through 16.2M gates (EPFL sixteen), after 3.1 s of elaboration. 8 GB laptop GPU.

202s

1,000,000 vectors through 93.4M gates: 19.2 s to elaborate, 182.6 s to simulate. Same laptop.

15:56min

200M gates, 16 vectors × 5,000 cycles, and a SAIF file covering all 200M nets. Same laptop.

10.7Bgates

in one connected chip split across four GPUs, checked against its C model. 10B on a single GPU, 2B on the 8 GB laptop. Next: 20B on eight GPUs.

Test generation and fault simulation

206Mgates

632 million stuck-at faults in one run: 99.49% test coverage with 5,112 vectors in 15.9 hours, on the 8 GB laptop GPU. How →

8min

Vortex 1c, 2.25M gates and 6.3M faults: 99.83% test coverage, 18,900 vectors. Same laptop.

12min

Vortex 2c, 3.80M gates and 12.3M faults: 99.21% test coverage, 16,800 vectors. Same laptop.

100%

of the faults counted untestable carry a proof that no test exists.

The simulator

Xerolane evaluates the synthesized netlist, gates and flip-flops, cycle by cycle. It sits after synthesis, where every design is re-verified for correctness, reset and X behaviour, coverage and sign-off, and where runtime is the bottleneck.

Many vectors at the same time

A sweep costs close to one run

Independent vectors simulate together on one GPU. How many run at once is a runtime setting.

2-state and 4-state

0, 1, X and Z

Full 4-state for reset, initialization and contention. A faster 2-state path for volume regression. Several clock domains, both edges.

Elaborate once

Simulate many

Elaboration is cached against the netlist and build, so later runs of the same design go straight to simulation.

Measured

Laptop figures are from an RTX 4060 with 8 GB, 24 CPU cores and 64 GB RAM, a machine under $2,000. EPFL designs are from the public EPFL Combinational Benchmark Suite; the enlarged ones use ABC's double.

Time for a workload, by design size

Design	Gates	Workload	Elaboration	Simulation	Machine
Synthetic, sequential	2,000,000	10,000 cycles	0.28 s	3.7 s	Laptop
EPFL sixteen	16,216,836	640,000 vectors	3.1 s	16.6 s	Laptop
EPFL sixteen	16,216,836	640,000 vectors	5.4 s	6.8 s	L40, rented pod
EPFL twentythree ×2	46,680,504	1,000,000 vectors	9.3 s	88.0 s	Laptop
EPFL twentythree ×4	93,360,248	1,000,000 vectors	19.2 s	182.6 s	Laptop
Synthetic, 20M flip-flops	200,000,128	16 vectors × 5,000 cycles, SAIF of every net	42 s	15 min 56 send to end	Laptop

Capacity, by card

Card	Largest design run	GPU memory used
RTX 4060 laptop, 8 GB	2 billion gates, 2-state and 4-state	1B gates in 7.7 GB
RTX 4090, 24 GB	500 million gates	12.6 GB
NVIDIA L40S, 48 GB	5.02 billion gates, every output checked	39.5 GB
NVIDIA RTX PRO 6000, 96 GB	4.40 billion gates, 575 million flip-flops, every flip-flop checked	43.7 GB
NVIDIA B200, 183 GB	200 million gates, many vectors	15.8 GB
NVIDIA B200, 183 GB	10.03 billion gates, 1.31 billion flip-flops, every output and flip-flop checked	101.6 GB
4 × NVIDIA L40S, 48 GB each	10.67 billion gates in one connected chip, split across the four, 64 data sets checked	2.67 billion gates on each card

Every design past 2 billion gates, and how each was checked →

Correctness: byte-identical to independent reference simulators

Design or suite	Scope	Reference	Result
Caravel management SoC, as signed off	67K gates, 3 stimulus sets, 42,000 clocks	Icarus Verilog, SkyWater cell models	Byte-identical
NVDLA	736K gates, 201 RAMs, 10,624 cycles	GEM	Byte-identical
Vortex, RISC-V GPGPU	2.25M gates, 64 vector sets of 10,000 cycles	Verilator	64 of 64 byte-identical
CVA6, 64-bit RISC-V application core	473K gates and 72 RAMs, built from its unedited SystemVerilog, 4,000 clocks	Verilator on the RTL	Byte-identical
Vortex, 16 cores	8.58M gates and 5,394 RAMs, built from its SystemVerilog, 512 stimulus sets of 2,000 clocks	Verilator on the RTL	512 of 512 byte-identical
EPFL sixteen	16.2M gates, 640,000 vectors	Verilator, aigsim	Every vector exact
LogikBench RTL corpus	159 designs, from RTL through Yosys	Icarus Verilog	Byte-identical
ISCAS'85/'89, EPFL, LGSynth, MCNC	2-state and 4-state	aigsim	No mismatches

Every design, its source and how it was compared →

From SystemVerilog to gates, checked against the RTL →

What it does

Every flow runs on the same engine, the same netlist and the same vectors.

Multiple clock domainsSeveral clocks, unrelated or derived, per-flop clock assignment, both edges, and memories in any clock domain.
4-state simulation0, 1, X and Z on every net, memories included, at twice the 2-state time.
Timed simulationPer-arc rise and fall delays, inertial pulse rejection, SDF back-annotation, VCD output.
Toggle coverageRecorded during simulation, at about 5% overhead.
Toggle counts and SAIFEvery net's full transition counts, memories included, written as SAIF for power analysis. Counting adds 15% to 37% to simulation time, depending on the design.
Save and restoreThree ways back in: replay, restart with fresh stimulus, or one saved state fanned out across many vectors. Coverage survives the restore.
Full state dumpEvery flip-flop and net, at any cycle.
DebugFind the first cycle and output where two runs part, trace an X back to where it came from, and export VCD for any window of cycles.
Stuck-at fault simulationCombinational and full-scan, many faults at once, with fault collapsing.
Test pattern generation (ATPG)Full-scan test vectors from the netlist alone, graded on the GPU: 99.49% test coverage over 632 million faults on a 206M-gate design in 15.9 hours, and 99.83% over 6.3 million faults on a 2.25M-gate RISC-V GPU core in 8 minutes, both on the 8 GB laptop. Results and the flow →
Design inputSystemVerilog and Verilog RTL from the project's own file lists (RTL to gates), gate-level Verilog, AIG and .bench.

Case studies

Public designs anyone can download, run from the netlist alone, with every number as measured.

Test generation · ITC'99

Every fault settled on b20 and b22, straight from the published netlists

ITC'99 is the benchmark set test-generation research measures on, published by Politecnico di Torino as .bench netlists. Xerolane read three of its larger circuits exactly as published and produced a full-scan stuck-at test set for each in one run, with the same settings for all three, on the 8 GB laptop.

b20 · 20.3K gates100%

test coverage, 41,763 faults, every one detected or proven untestable. 1,099 vectors in 169 s.

b22 · 30.1K gates100%

test coverage, 62,140 faults, every one detected or proven untestable. 1,101 vectors in 191 s.

b19 · 234K gates99.92%

test coverage, 486,533 faults. 2,301 vectors in 31 minutes.

Netlist to final vector set, one run per design

Design	Gates	Stuck-at faults	Test coverage	Vectors	Netlist to vectors
ITC'99 b20	20.3K	41,763	100.00%	1,099	169 s
ITC'99 b22	30.1K	62,140	100.00%	1,101	191 s
ITC'99 b19	234K	486,533	99.92%	2,301	31 min

The published netlist, gate for gateNo resynthesis or remapping, so every fault site is the one in the published file. The netlists are at github.com/cad-polito-it/I99T.
Full scan, collapsed stuck-at faultsStuck-at-0 and stuck-at-1 on every gate pin, equivalent faults collapsed, every flip-flop on a scan chain.
Untestable means provenA fault counts as untestable only with a proof that no test for it exists.
One laptopRTX 4060 with 8 GB, 24 CPU cores, 64 GB RAM.

Test coverage is detected faults divided by faults not proven untestable. On b19, 4.2% of the faults are proven untestable, so no tool can reach more than 95.8% fault coverage on it.

Gate-level simulation and power · our own design

A transformer inference chip, from 247 million gates on a laptop GPU to 2 billion on one datacentre GPU

An integer transformer datapath we wrote in Verilog, with a C program that defines every correct answer. At 246.8M gates, 64 independent data sets run 385,186 clock cycles in 6 h 38 min on the 8 GB laptop GPU, every output matching the reference byte for byte. Switching activity for all 246.8M nets costs 37% more time. The final chip, at 2.04 billion gates, ran 1.59 million cycles of 64 data sets on one NVIDIA L40S in 42 h 51 min, every data set matching. On a 277M-gate version with its weights in 2,304 memories, 4-state simulation took twice the 2-state time and a full SAIF 29% more; versions with four unrelated clocks, and with a RISC-V processor feeding the chip its work, match the reference too.

Read the case study: the design, the diagrams and every run →

Gate-level simulation · one design across GPUs

The same chip at 10.7 billion gates, split across four GPUs

With 1,024 experts in each of its 16 layers and its weights in memories, the transformer chip is 10.67 billion gates. Split by layers into four parts on four NVIDIA L40S cards in one rented machine, with the signals between the parts exchanged every clock cycle, it ran 64 data sets through 82,109 cycles in 5 hours, about $23 of GPU time, every data set matching its C model. Next: 20 billion gates on eight GPUs.

At 2.41 billion gates, four GPUs ran four times the data sets in the same time, or the same 64 data sets 3.97 times faster. Scaling two ways →

Read how the chip is split, and the run →

Running it

Xerolane installs as a set of binaries on a Linux machine with NVIDIA or AMD GPUs. Both produce identical traces on the same design and stimulus. A design too large for one GPU is split across the machine’s GPUs and runs as one. No compiler or GPU toolkit is needed on your side.

Your netlist stays on your machine.

Try it on your design

Send a netlist, or tell us its size and what you run on it today. We will come back with elaboration and simulation times for your workload.

Company

Xerolane Design Systems LLP is based in Noida, India.

Manu Lauria, founder

An IIT alumnus and former Cadence engineer with 24 years in EDA. He led the NCSim India team and then Xcelium R&D Operations.

Contact

Evaluations, partnerships and design data.

manu@xerolane.com