RTL to gates
From SystemVerilog to gates, checked against the RTL
Xerolane reads a project's SystemVerilog the way the project ships it: its file lists, packages, include paths, library directories and memory models. It elaborates the design, synthesises it to a gate netlist with the memories kept as memories, and runs that netlist on the GPU. The netlist does what the RTL does in a two-state simulator. Every design on this page was checked against Verilator running the RTL itself: every output, every cycle, the same bytes.
Vortex with 16 cores, built from its SystemVerilog: 1.35M flip-flops and 5,394 memories.
random stimulus sets on Vortex 16 cores identical to Verilator on the RTL, 2,000 clocks each.
from Vortex 16 cores' sources to a netlist ready to run, on a laptop.
faster than Verilator on the RTL using all 24 CPU threads, at 512 stimulus sets, simulating gates.
Designs built from RTL
Each design was read from its unedited sources, built to gates and simulated on Xerolane, then simulated as RTL on Verilator with the same stimulus. The outputs were compared on every cycle.
| Design | Gates | Stimulus | Against Verilator on the RTL |
|---|---|---|---|
| Vortex, 16 coresRISC-V GPGPU, one cluster with a shared L2 cache | 8,576,439 gates, 1,352,287 flip-flops, 5,394 memories | 512 random stimulus sets, 2,000 clocks each | 512 of 512 byte-identical |
| Vortex, 1 corethe same design with one core and no L2 | 446,659 gates, 59,307 flip-flops, 258 memories | 2,000 clocks of random stimulus | Byte-identical |
| CVA6OpenHW Group's 64-bit RISC-V application core, cv64a6_imafdc_sv39, from its own file list | 472,629 gates, 26,980 flip-flops, 72 memories | 4,000 clocks of random stimulus | Byte-identical |
| PicoRV32a small RISC-V CPU | 7,668 gates, 2 memories | 4,000 clocks of random stimulus | Byte-identical |
What it reads, and how
- The project's own file lists-f and -F lists, nested, with environment variables in the paths; -v library files and -y library directories with +libext+; include directories and defines. Only the modules the top uses are read, so an unused file that would not compile does no harm.
- What a simulator readssynthesis translate_off regions are read, as simulators read them, so a memory model inside its wrapper is simulated. full_case and parallel_case are honoured.
- Testbench code left outAssertions, $display and file tasks, and initial blocks that are testbench code are left out of the gates, each with a warning. An initial block that sets start values is kept.
- Memories stay memoriesArrays become the engine's memories, up to 8,192 words of 32 bits with a write enable per bit, rather than flip-flops. Wider and deeper arrays are built from several.
- Two-state, as Verilator runs itEvery register and memory starts at 0, and an x the RTL assigns, or a bit nothing drives, is 0: the values Verilator gives with --x-initial 0 --x-assign 0.
- The same sources on both sidesThe reference run reads the very copies the build read, in the same order, with the same include paths and defines, so the comparison checks the build, not two readings of the sources.
Speed against Verilator on the RTL
Vortex with 16 cores, 2,000 clocks, on one laptop: an NVIDIA RTX 4060 Laptop GPU and an Intel Core i7-14650HX with 16 cores and 24 threads. Xerolane simulates the 8.58 million gates; Verilator simulates the RTL, which is far less work per cycle.
| Stimulus sets | Verilator on the RTL | Xerolane on the gates |
|---|---|---|
| 1 | 1.39 s on one thread, 0.43 s on 8 threads | 2.6 s |
| 64 | about 7.7 s, 24 at a time on every thread | 5.6 s, all 64 together |
| 512 | about 70 s, 24 at a time on every thread | 31.8 s, all 512 together |
Simulation time. Every one of the 512 stimulus sets gave the same outputs on both.
Xerolane runs 64 stimulus sets in about twice the time of one, and 512 in under six times that, so its advantage grows with the number of tests: a regression, a random-stimulus campaign, a fault simulation. At 512 sets it simulates 8.58 million gates for 2,000 clocks in 62 ms a set, against 137 ms for Verilator on the RTL with the whole CPU. For a single test on a design this size, Verilator on the RTL is faster.