Large designs
Billions of gates, on one GPU or several, every result checked
Xerolane simulates designs of billions of gates on a single GPU, and splits larger ones across several. Every run on this page was checked against an independent reference: a C model of the design, the aigsim reference simulator, or the original design the copies were made from.
in one connected chip, split across four GPUs: 64 data sets against its C model. How →
on one GPU, 1.31 billion flip-flops: every output and every flip-flop of every copy checked.
in one connected chip, 1.59 million cycles of 64 data sets against its C model.
on any design listed here.
Designs and their checks
One row per run. The check column names what Xerolane's results were compared with.
| Design | Size | Run | Checked against | GPU | Result |
|---|---|---|---|---|---|
| Transformer inference chip, across four GPUs1,024 experts × 16 layers, one connected design, weights in memories | 10.67 billion gates, 2.67 billion on each GPU | 82,109 cycles × 64 data sets, 5 h 1 min | The design’s C reference model, every data set | 4 × NVIDIA L40S, 48 GB each | 64 of 64 exact |
| 1,200 copies of a neural-network chipone expert by one layer of the transformer chip | 10.03 billion gates, 1.31 billion flip-flops | 2,000 cycles in 216 s; eight runs at once in 205 s | The original design: every output, and every flip-flop’s saved state | NVIDIA B200, 183 GB | 1,200 of 1,200 exact |
| Transformer inference chip16 experts × 16 layers, one connected design | 2.04 billion gates, 276 million flip-flops | 1.59 million cycles × 64 data sets, about 43 hours | The design's C reference model, every data set | NVIDIA L40S, 48 GB | 64 of 64 exact |
| 178 copies of EPFL twentythreeEPFL Combinational Benchmark Suite | 5.02 billion gates | 100 cycles | aigsim, every output of every copy | NVIDIA L40S, 48 GB | 178 of 178 exact |
| 160 copies of EPFL twentythree | 4.51 billion gates | 100 cycles | aigsim, every output of every copy | NVIDIA L40S, 48 GB | 160 of 160 exact |
| 527 copies of a neural-network chipone expert by one layer of the transformer chip | 4.40 billion gates, 575 million flip-flops | 2,000 cycles | The original design: every output, and every flip-flop’s saved state | NVIDIA RTX PRO 6000, 96 GB | 527 of 527 exact |
How the copies make one design
The copies sit side by side in one netlist, with no wires between them. Each has its own inputs and outputs, and all of them run on one shared clock. Every copy is driven with the original design’s input vectors, so every copy must reproduce the original’s outputs, cycle for cycle. No reference simulator can run a 10-billion-gate design whole, but each copy can be checked against one that has already checked the original.
The transformer chip, by contrast, is one connected design: its experts and layers are wired together into a working chip, and its results are checked against the C model it was built from. At 2.04 billion gates it ran on one GPU; at 10.67 billion it was split across four, exchanging the signals between the parts every clock cycle.
Past 4.29 billion
- 40-bit gate idsA 32-bit id stops at 4,294,967,296 gates. Xerolane’s ids are 40 bits, and the four runs past that line check every output, and every flip-flop, beyond it.
- Saved state, checkedA design’s flip-flops can be saved at any cycle and restored later. On the 4.40-billion-gate run, the state of all 575 million flip-flops was saved and compared with the original design’s; on the 10.03-billion-gate run, all 1.31 billion.
- Host memoryPreparing a design for simulation takes about 22 bytes of host memory a gate: 113 GB for the 5.02-billion-gate design. Now about 18 bytes: 185 GB for the 10.03-billion-gate design.
- GPU memoryThe 5.02-billion-gate design used 39.5 GB of a 48 GB card; the 4.40-billion-gate design, with its flip-flops, 43.7 GB of 96 GB; the 10.03-billion-gate design, 101.6 GB of 183 GB, the same for one run as for eight at once.