Test generation and fault simulation
Test vectors from the netlist alone, graded on the GPU
Xerolane takes a gate-level netlist and produces a full-scan stuck-at test set in one run: it generates the vectors, grades every one against the whole fault list on the GPU, and proves the faults no vector can detect. Nothing is carried over from earlier runs, and every result on this page comes from a single laptop.
206M gates and 632M faults: 99.49% test coverage, 5,112 vectors, on the 8 GB laptop GPU.
Vortex 1c, 2.25M gates and 6.3M faults: 99.83% test coverage, 18,900 vectors.
Vortex 2c, 3.80M gates and 12.3M faults: 99.21% test coverage, 16,800 vectors.
of the faults counted untestable carry a proof that no test exists.
Results
Each row is one run from the gate-level netlist; the 206M-gate and Vortex runs stop once test coverage passes 99%, and the ITC’99 runs go to the end. Test coverage is detected faults divided by the faults not proven untestable.
| Design | Gates | Flip-flops | Stuck-at faults | Test coverage | Vectors | Proven untestable | Netlist to vectors |
|---|---|---|---|---|---|---|---|
| Transformer inference chip | 206M | 15,722,920 | 632,360,807 | 99.49% | 5,112 | 33,529,304 | 15 h 53 min |
| Vortex 1c, RISC-V GPGPU | 2,248,738 | 527,622 | 6,314,931 | 99.83% | 18,900 | 217,942 | 8 min 11 s |
| Vortex 2c, RISC-V GPGPU | 3,798,010 | 1,025,654 | 12,268,119 | 99.21% | 16,800 | 298,002 | 11 min 51 s |
| ITC'99 b19 | 234K | — | 486,533 | 99.92% | 2,301 | — | 31 min |
| ITC'99 b22 | 30.1K | — | 62,140 | 100.00% | 1,101 | — | 191 s |
| ITC'99 b20 | 20.3K | — | 41,763 | 100.00% | 1,099 | — | 169 s |
Laptop: NVIDIA RTX 4060 with 8 GB, 24 CPU cores, 64 GB RAM. Fault counts are after equivalence and dominance collapsing. The 206M-gate design ran as eight subdesigns of up to 27M gates each, every list, vector and result kept in the whole design's terms.
We first published Vortex 1c and 2c in September 2026: 99.19% test coverage with 18,495 vectors in 15 hours, and 99.29% with 18,204 vectors in 32 hours, on the same laptop. The runs above are 110 to 160 times faster, from better algorithms and from moving more of the test generation and fault simulation onto the GPU.
The flow
- From the netlist aloneThe run starts from the gate-level netlist, as a customer would hand it over. The fault list, the scan model and everything else are built from it.
- Full scan, collapsed stuck-at faultsStuck-at-0 and stuck-at-1 on every gate pin, equivalent and dominated faults collapsed, every flip-flop on a scan chain. Outputs are read in the cycle after capture.
- Generation and grading togetherVectors are built in stages. Each stage is graded against every fault still undetected, and what it detects is never searched for again, so most faults are caught by vectors built for others.
- Untestable means provenA fault leaves the coverage denominator only with a proof that no test for it exists.
- Every credited fault checkedFaults dropped by dominance collapsing are graded against the final vectors at the end of the run; on both Vortex runs every one sampled was detected.
- Larger designsThe 206M-gate run is on our own transformer inference chip. Designs are split into subdesigns, so memory follows the largest subdesign, not the design; runs at 500 million gates and beyond are next.
Open designs and tools
These results stand on open work: Vortex, the RISC-V GPGPU from Georgia Tech; Yosys, which took its RTL to gates; the ITC'99 benchmarks from Politecnico di Torino; and Armin Biere's CaDiCaL SAT solver. Our thanks to all of them.