Verification
Checked against independent simulators, byte for byte
Every design on this page is public. Each was simulated on Xerolane and on an independent reference simulator, from the same netlist and the same stimulus, and every output was compared on every cycle. Not close, not statistically equivalent: the same bytes. Anyone can download the design and the reference simulator and repeat the comparison.
independent references: Icarus Verilog, Verilator, aigsim and GEM.
the largest design checked against two references, 640,000 vectors, every vector exact.
of the LogikBench RTL corpus, from RTL through Yosys, byte-identical.
on any design listed here.
Designs and their references
One row per design or suite. The reference column names the simulator Xerolane was compared with; the stimulus column says how much was run.
| Design | Size | Reference simulator | Stimulus | Result |
|---|---|---|---|---|
| Caravel management SoCEfabless, SkyWater sky130, as signed off after place and route | 67,153 gates, 4,790 flip-flops, two SRAM macros | Icarus Verilog, running the original netlist with SkyWater's own cell models | 3 random stimulus sets, 42,000 clocks | Byte-identical |
| NVDLANVIDIA's open deep-learning accelerator | 736K gates, 94,262 flip-flops, 201 RAMs | GEM, NVIDIA's open-source GPU gate-level simulator | 10,624 cycles, GEM's golden trace | Byte-identical |
| Vortex, 1 coreRISC-V GPGPU, RTL through Yosys | 2.25M gates | Verilator | 64 stimulus sets × 10,000 cycles | 64 of 64 byte-identical |
| EPFL sixteenEPFL Combinational Benchmark Suite, MtM set | 16,216,836 gates | Verilator, and aigsim | 640,000 vectors | Every vector exact, on both |
| EPFL twenty and twentythreeEPFL suite, MtM set | 20.7M and 23.3M gates | aigsim | 640,000 vectors each | Every vector exact |
| LogikBench RTL corpusZero ASIC, RTL through Yosys | 159 designs | Icarus Verilog, running the Verilog Yosys wrote | Random setup-hold stimulus per design | 159 of 159 byte-identical |
| AES-128 and PicoRV32RTL through Yosys | Two RTL designs, a cipher and a CPU | Icarus Verilog | 4-state, X propagation included | Byte-identical |
| ISCAS'85, ISCAS'89, EPFL, LGSynth, MCNCthe classic logic benchmark suites, through ABC and AIGER | The suites' circuits | aigsim | 2-state and 4-state | No mismatches |
| sky130 SRAM, 1 KB, one read-write and one read portcompiled by OpenRAM, read from its Liberty file | 256 words × 32 bits | Icarus Verilog, with OpenRAM's own Verilog model | 20,000 random cycles | Every defined output bit equal |
How a comparison is run
- The same netlist and the same stimulusBoth simulators read the design and the input vectors from the same files. Nothing is retuned for one side.
- Every output, every cycleOutput traces are compared as files, byte for byte. One bit in one cycle is a mismatch.
- The reference reads the design its own wayOn the RTL suites the reference runs the Verilog that Yosys wrote, while Xerolane runs a netlist built through its own converter, so a match checks the conversion as well as the simulation. On Caravel the reference runs the foundry's cell models; Xerolane reads the cells' logic from the Liberty file.
- X and Z countIn 4-state runs an X where the reference has a 0 is a mismatch like any other.
Reference simulators
- Icarus VerilogAn event-driven Verilog simulator, the long-standing open-source reference for Verilog semantics.
- VerilatorCompiles Verilog into C++ for fast cycle-based simulation.
- aigsimThe reference simulator of the AIGER toolkit, for and-inverter graphs.
- GEMNVIDIA's open-source GPU gate-level simulator.
Xerolane's own engines are held to the same bar against each other: the CPU reference and the GPU engine, NVIDIA and AMD GPUs, and every internal execution strategy produce identical traces.