Test generation · 31 October 2026
ATPG and fault simulation at half a billion gates, on one GPU
Two capacity results from Xerolane’s ATPG and fault-simulation flow. Each run starts from the gate-level netlist alone, as a customer would hand it over, and ends with a graded vector set: 206 million gates on a laptop GPU, and 515 million gates on one data-centre GPU.
1.79 billion collapsed stuck-at faults, 99.48% test coverage, 5,575 vectors, on one NVIDIA L40S.
for the 515M-gate design, from its netlist to the graded vector set.
715 million collapsed stuck-at faults, 99.49% test coverage, 5,112 vectors, on an 8 GB laptop GPU.
for the 206M-gate design, from its netlist to the graded vector set.
Results
Each row is one run of the same flow with the same settings. A run stops once test coverage passes 99%. Test coverage is detected faults divided by the faults not proven untestable, and a fault counts as untestable only with a proof that no test for it exists.
| Design | GPU | Gates | Flip-flops | Stuck-at faults | Test coverage | Vectors | Netlist to vectors |
|---|---|---|---|---|---|---|---|
| Transformer inference chip | NVIDIA L40S, 48 GB | 514,989,133 | 39.3M | 1,785,399,853 | 99.48% | 5,575 | 21 h 12 min |
| Transformer inference chip | RTX 4060 laptop, 8 GB | 206M | 15,722,920 | 714,799,501 | 99.49% | 5,112 | 15 h 53 min |
Fault counts are stuck-at-0 and stuck-at-1 on every gate pin, after equivalence collapsing. Times are wall-clock, as measured. Laptop: RTX 4060 with 8 GB, 64 GB RAM.
The designs
Both designs are instances of our own transformer inference chip, generated at each size. They are whole chips rather than copies of one block: clock-domain crossings, RAMs, a control processor, and a C reference model the chip is checked against.
- From the netlist aloneEach run starts from the gate-level netlist. The fault list, the scan model and everything else are built from it; nothing is carried over from an earlier run.
- Full scan, collapsed stuck-at faultsEvery flip-flop on a scan chain, stuck-at-0 and stuck-at-1 on every gate pin, equivalent faults collapsed.
- Untestable means proven83 million faults on the 515M-gate design and 34 million on the 206M-gate design left the denominator, each with a proof that no test exists.
- One GPU eachThe 206M-gate run used one 8 GB laptop GPU, the 515M-gate run one L40S. The same flow, unchanged, ran on both.
Next
One billion gates, across several GPUs. Results from smaller designs, and how the flow runs, are on the test generation page.